View IP1206TRPBF_4944786.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PD-60319
iP1206PbF
Synchronous Buck Multiphase Optimized LGA Power Block
Features
* * * * * * * * * * * *
Integrated Power Semiconductors, PWM Control, & Passives
Input voltage range of 7.5V to 14.5V Output voltage range of 0.8V to 5.5V Output voltage accuracy of +/-1% Output current range of 0A to 30A Operation up to 600kHz Lossless current limit Output overvoltage protection Pre-Bias start-up External synchronization Output voltage tracking Output voltage sequencing Over temperature protection
Description
The iP1206 is a fully optimized solution for medium current synchronous buck applications. The iP1206 can be configured as a dual output voltage power supply delivering up to 15A of current per output. Alternatively, the iP1206 can be configured as a single output voltage power supply delivering up to 30A of current. In both cases, the power stages are operated 180 out of phase. This reduces the amount of input RMS current and lessens the quantity of input capacitors needed. iPOWIR Technology offers designers an innovative board space saving solution for applications requiring high power densities. iPOWIR technology eases design for applications where component integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat transfer, and component selection.
Applications
* * * * * Embedded Telecom Systems Distributed Point of Load Power Architectures Powering Dual Voltage ASICs Microprocessor Power Supplies General DC/DC Converters
Package Description iP1206PbF IP1206TRPBF Interface Connection LGA LGA Parts Per Bag 10 Parts Per Reel 750 T&R Orientation Fig. 29
Typical Application
Dual Output
Single Output
www.irf.com
2/26/2008
1
iP1206PbF
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND)
*VIN1, VIN2, VCC, VCL Supply Voltage ...................... -0.3V to 16V *VCH ......................................................... -0.3V to 30V *VSW1,2 ...................................................... -0.3V to 30V *FB1,2 ....................................................... -0.3V to 3V *VP-VREF ................................................... -0.3V to 3V *ENABLE .................................................... -0.3V to Vcc *OC1,2 ...................................................... -0.3V to 3V *SS1,2 ...................................................... -0.3V to 3V *TRACK, SEQ ............................................. -0.3V to Vcc *RT .......................................................... -0.3V to 3V *PGOOD1, PGOOD2 .......... .............................. -0.3V to Vcc *AGND to PGND .......................................... +/- 0.3V *Storage Temperature Range ................................. -65C To 150C *Block Temperature........................... ................ -20C To 125C (Note 4) *ESD Classification ...................................... JEDEC, JESD22-A114 (HBM[1KV], Class 1C) ...................................... JEDEC, JESD22-A115 (MM[50V], Class A) *MSL Rating ................................................... 3
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those listed in the "Recommended Operating Conditions" section of this specification is not implied.
Package Pinout Diagram
FB2 35 CC2 1 SS2 2 FB2S 34 RT 33 NC 32 ENABLE TRACK 31 30 VO3 29 VCC 28 PGOOD1 VREF 27 26 VP2 25 VP1 24 PGOOD2 SYNC 23 22 SEQ 21 FB1S 20 FB1 19 CC1 18 SS1 17
VIN2 3
AGND 36
VIN1 16
PGND 4
VSW2 5
PGND 6
PGND 13
VSW1 14
PGND 15
VCB2 7
OC2 8
VCH 9
VCL 10
OC1 11
VCB1 12
www.irf.com
2/26/2008
2
iP1206PbF
Recommended Operating Conditions
Symbol
VIN1, VIN2 VCC Io (Note1) Fs Tj
Definition
Input Supply Voltage Bias Supply Voltage Output current per Phase Operating frequency Junction temperature
Min
7.5 7.5 0 200 -40
Max
14.5 14.5 15 600 125
Units
V V A kHz o C
Electrical Specifications
Unless otherwise specified, these specification apply over Vcc=12V, 0oCPARAMETER
Supply Power
Power Loss VIN Supply Current (Static) VCC Supply Current (Static) VCH Supply Current (Static)
Min
Typ
Max
Units
Conditions
-
5 0.5 25 10
6.5 2 30 12
W mA mA mA
VIN = 12V, VO1 = V02 = 1.5V, IO1 = IO2 = 15A, fSW = 300kHz, TBLK = 25C VIN = 12V, ENABLE = 0V SS=0V ; no switching; Vcc tied to VCL SS=0V ; no switching
Power-On Reset (POR)
VCC Rising VCC Falling Hysteresis 6.9 6.1 500 7.5 6.75 V V mV VIN Rising & Falling
DC Output Regulation
0.792 System Set Point Accuracy 0.784 0.8 0.810 V TJ = -40C to 125 (Note 2) 0.8 0.808 V TJ = 0C to 105C (Note 2)
Enable
Turn-on Threshold (VIH) Hysteresis 1.14 150 1.34 V mV Rising & Falling
Soft Start 1,2
Voltage Level Disable Voltage Level Sink/Source Current 18 3.0 23 0.25 28 V V A VIN = ENABLE = 12V
www.irf.com
2/26/2008
3
iP1206PbF
Electrical Specifications
PARAMETER
Error Amplifier 1,2
Input Bias Current Sink/Source Current Transconductance Input Offset Voltage VP pin Voltage Range TRACK pin Voltage Range 120 3000 -3.5 0.4 0 -0.1 200 -0.5 280 5000 3.5 VCC - 2 VO 3 A A mho mV V V FB to Vref (Note 3) (Note 3) Soft Start Pin = 3V
Min
Typ
Max
Units
Conditions
Oscillator
Frequency Range Frequency Accuracy Ramp Amplitude Minimum Duty Cycle Maximum Duty Cycle Minimum Pulse Width SYNC Frequency Range SYNC Pulse Duration SYNC HIGH Level Threshold (VIH) SYNC LOW Level Threshold (VIL) 200 88 84 200 2 1.25 300 600 112 0 150 1200 0.6 kHz % V % % ns kHz ns V V FB = 1V FS = 300kHz, FB = 0V FS = 300kHz 20% above Free Running Freq FS = 300kHz
Sequence
Turn on Threshold Turn off Threshold 0.3 5 V V
POWER GOOD Monitor
FB1/2S Threshold PGOOD1/2 Output Low Voltage 80 90 0.1 95 0.5 % V Percentage of Voltage Reference ISINK = 2mA
Over Voltage Protection
Start Threshold Propagation Delay to Shutdown 110 115 120 5 % s Percentage of Voltage Reference Output Voltage set to 1.25Vref (Note3)
www.irf.com
2/26/2008
4
iP1206PbF
Electrical Specifications
PARAMETER
Over Current Protection
Start Threshold Hiccup Duty Cycle 20 24.5 5 29 A % VIN = 12V, ROCSET = 7.5K (Note 3)
Min
Typ
Max
Units
Conditions
Thermal Shutdown
Start Threshold Temperature Hysteresis 130 145 20 C (Note 3) C
Internal Regulator (VO3)
Output Accuracy Dropout Voltage Current Limit 110 6.7 7.2 7.7 2 V V mA VCC = 12V, ILOAD = 50mA VCC = 9V, ILOAD = 100mA
Note1: Continuous output current determined by input and output voltage setting. Refer to SOA curve. Note2: FB1,2 connected to CC1,2. Measured at the CC1,2 pin. Production tested at 25C. Other temperatures guaranteed by design. Note3: Guaranteed by design but not tested in production. Note4: Block Temperature is defined as any Die temperature within the package.
www.irf.com
2/26/2008
5
iP1206PbF
Pin Description
Pin Number
1 2 3 4, 6, 13, 15 5 7 8 9 10 11 12 14 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Pin Name
CC2 SS2 VIN2 PGND VSW2 VCB2 OC2 VCH VCL OC1 VCB1 VSW1 VIN1 SS1 CC1 FB1 FB1S SEQ SYNC PGOOD2 VP1 VP2 VREF PGOOD1 VCC VO3 TRACK ENABLE NC RT FB2S FB2 AGND Compensation pin for Error Amplifier 2 Soft Start/Shutdown pin for output 2
Description
Input supply voltage connection to output 2 Power Ground Voltage Switching Node for output 2 - pin connection to the output inductor Boot strap capacitor pin for output 2 - connect a 0.1F from this pin to VSW2 Over current threshold setting pin for output 2 Supply voltage for internal high side FET drivers of both outputs Supply voltage for internal low side FET drivers of both outputs Over current threshold setting pin for output 1 Boot strap capacitor pin for output 1 - connect a 0.1F from this pin to VSW1 Voltage Switching Node for output 1 - pin connection to the output inductor Input supply voltage connection to output 1 Soft Start/Shutdown pin for output 1 Compensation pin for Error Amplifier 1 Inverting input for Error Amplifier 1 Output over voltage protection sense pin for output 1 Sequence Enable pin External clock synchronization pin - when not in use, leave pin floating Power Good status pin of output 2 - output is open collector Non-inverting input of error amplifier 1 Non-inverting input of error amplifier 2 Internal voltage reference pin - connect a 100pF from this pin to AGND Power Good status pin of output 1 - output is open collector Input supply voltage of internal control IC - connect a 1.0F from this pin to AGND Output of internal regulator used to supply VCH - connect a 1.0F from this pin to PGND Secondary non-inverting input to Error Amplifier 2 - used to set the type of power up/down sequence of the output voltages Master enable pin. Recycling this pin will reset OV, SS, and Pre-Bias latch for both outputs. No connect. This pin is not for electrical connection. Switching frequency setting pin Output over voltage protection sense pin for output 2 Inverting input for Error Amplifier 2 Analog Ground
www.irf.com
2/26/2008
6
iP1206PbF
Block Diagram
Enable Vcc
25uA 25uA 64uA Max 64uA Mode Bias Generator UVLO 0.3V
S S Q R Q R
SS2 POR POR 0.3V
SS1 3V 0.8V
PBias1
PBias2
SS2 / SD SS1 / SD
POR
VCB1 VCB2
VCH1 VCH2
POR PWM Comp1 Error Amp1
VCH VIN1
P1 V
Fb1
Ramp1
Thermal Shutdown
VSW1 PGND
CC1 Rt Sync
REF V 0.8V Error Amp2 Ramp2
Two Phase Oscillator
Driver
VIN2
VSW2
PWM Comp2
PGND
OVP1 OVP2
Track
P2 V
Fb2 CC2 FBS1 FBS2
20uA PGood / OVP
VCL SS1
3uA
PBias1 OC1
PGood1 PGood2 Seq
O3 V Regulator Tracking
SS1 SS2 Hiccup Control Mode
SS1 / SD
SS2
3uA
OC2
20uA
AGnd
Fig. 2: Simplified block diagram of the iP1206
www.irf.com
2/26/2008
7
iP1206PbF
TYPICAL OPERATING CHARACTERISTICS
16 15 14 13 12
Output Current per Channel (A)
11 10 9 8 7 6 5 4 3 2 1 0 0 10 20
Safe Operating Area
VI = 12V VO1 = VO2 = 1.5V Fsw = 300kHz LO = 1.0H
30
40
50
60
70
80
90
100
110
120
130
PCB Temperature (C)
Fig. 3: Safe Operating Curve
11 10 9 Total Power Loss, Both Outputs (W) 8 7 Maximum 6 5 Typical 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Output Current per Channel (A)
VI = 12V VO1 = VO2 = 1.5V Fsw = 300kHz LO = 1.0H T BLK = 125C
Fig. 4: Power Loss vs. Output Current
www.irf.com
2/26/2008
8
iP1206PbF
TYPICAL OPERATING CHARACTERISTICS
1.70 19.5
1.60 13.5
1.60
16.7
1.50
1.50
13.9
Normalized Power Loss
1.40
11.1
Normalized Power Loss
1.40
VI = 12.0V IOUT = 30A FSW = 300KHz LO = 1H T BLK = 125C
11.3
SOA temperature adjustment (deg. C)
SOA Temp Adjustment( deg. C)
9.0
1.30
6.8
1.30
8.4
1.20
4.5
1.20
5.6
1.10 2.3
1.10
1.00
0.90
VO = 1.5V IO = 30A FSW = 300KHz LO = 1H T BLK = 125C
2.8
1.00
0.0
0.0
0.90
-2.3
-2.8
0.80 7 8 9 10 11 12 13 14 15
-5.6
0.80 0.8 1.5 2.2 2.9 3.6 4.3 5.0 5.7
-4.5
Input Voltage(V)
Output Voltage (V)
Fig. 4a: Power Loss vs. Input Voltage
Fig. 4b: Power Loss vs. Output Voltage
1.6
1.72
19.8
VI = 12.0V
1.5
VO = 1.5V IOUT = 30A LO = 1H TBLK = 125C
10.8
1.64
VI = 12.0V VO = 1.5V IOUT = 30A FSW = 300KHz TBLK = 125C
17.6
SO A T em p Adjustm ent ( 0 C)
1.4
8.7
Norm alized Power Loss
SOA Temp Adjustment (C)
Normalized Power Loss
1.56
15.4
1.48
13.2
1.3
6.5
1.40
11.0
1.2
4.3
1.32
8.8
1.1
2.2
1.24
6.6
1.0
0.0
1.16
4.4
0.9
-2.2
1.08
0.8 200 -4.3 600
2.2
300
400
500
1.00 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0.0
Switching Frequency (kHz)
Output Inductance (H)
Fig. 4c: Power Loss vs. Switching Frequency
Fig. 4d: Power Loss vs. Output Inductor
95 Max Duty Cycle (%) 90 85 80 75 70 65 200 250 300 350 400 450 500 550 600 Switching Frequency (KHz)
Fig. 5 Maximum Duty Cycle vs. Switching Frequency
www.irf.com
2/26/2008
9
iP1206PbF
Circuit Description
THEORY OF OPERATION Introduction
The iP1206 is a versatile device for high performance buck converters. It consists of two synchronous buck controllers which can be operated either in a two independent outputs mode or in a current share single output mode for high current applications. The timing of the IC is provided by an internal oscillator circuit which generates two-180o-out-ofphase clock that can be externally programmed up to 600kHz per phase.
Enable
The enable features another level of flexibility for start up. The Enable has precise threshold which is internally monitored by an under-voltage lockout circuit. It's threshold can be externally programmed to desired level by using two external resistors, so the converter doesn't start up until the input voltage has reached the specified threshold level (see Fig. 6).
Under-Voltage Lockout
The under-voltage lockout circuit monitors four signals (Vcc, Enable, VCH1, VCH2). This ensures the correct operation of the converter during power up and power down sequence. The driver outputs remain in the off state whenever one of these signals drops below set thresholds. Normal operation resumes once these signals rise above the set values. Fig. 6 shows a typical start up sequence.
12V 11V 12V
7.25V
7.2V
VIN Vbus
Vcc
Vout3 Vcc OK Enable OK (IC's POR) 3V Enable SS
Seq
Fig. 6: Normal Start up, Enable threshold is externally set to 11V Seq pin is pulled high prior to start up
www.irf.com
2/26/2008
10
iP1206PbF
Internal Regulator
iP1206 features an on-board regulator capable of sourcing current up to 100mA. This integrated regulator can be used to generate the necessary bias voltage for drivers. An example of how this can be used is shown in Fig. 25. The output of the regulator is protected for short circuit and thermal shutdown. In addition, the 180o out of phase operation contributes to input current cancellation. This results in a much smaller input capacitor - RMS current thereby reducing the input capacitor quantity. Fig. 8 shows the equivalent RMS current. RMS Current Normalized (IRMS/Iout)
Single Phase
Out-of-Phase Operation
The iP1206 drives its two output stages 180o outof-phase. In current share mode (single output), the two inductor ripple currents cancel each other and result in a reduction of the output current ripple and yield a smaller output capacitor for the same ripple voltage requirement. Fig. 7 shows two channels inductor current and the resulting voltage ripple at output.
2 Phase
Duty Cycle (Vo/Vin)
HDRV1
Fig. 8: Input RMS value vs. Duty Cycle
Mode Selection
0 DT T
HDRV2
IL1
IL2
The iP1206 can operate as a dual output independently regulated buck converter, or as a 2 phase single output buck converter (in current share mode). The SS2 pin is used for mode selection. In current share mode this pin should be floating and in dual output mode a soft start capacitor must be connected from this pin to ground to program the start time for the second output.
Independent Mode
Ic
Io
Fig. 7: Current ripple cancellation for output
In this mode the iP1206 provides control to two independent output power supplies with either common or different input voltages. The output voltage of each individual channel is set and controlled by the output of the error amplifier, which is the amplified error signal from the sensed output voltage and the reference voltage. The error amplifier output voltage is compared to the ramp signal thus generating fixed frequency pulses of variable duty-cycle, (PWM) which are applied to the internal MOSEFT drivers. Fig. 25b shows a typical schematic for such an application.
www.irf.com
2/26/2008
11
iP1206PbF
Current Share Mode
This feature allows the connection of both outputs together to increase current handling capability of the converter to support a common load. In current sharing mode, error amplifier 1 becomes the master which regulates the common output voltage and the error amplifier 2 performs the current sharing function, Fig. 9 shows the configuration of error amplifiers. See Fig 25a for a typical application. In this mode iP1206 makes sure the master channel starts first followed by slave channel to prevent any glitch during start up. This is done by clamping the output of slave's error amplifier until the master channel generates the first PWM signal. At no load condition the slave channel may be kept off depending on the offset of error amplifier.
Vin
Master Phase
IL1 L1 + RL1 VL1 (s) C1 + VC1(s) VP2 VOUT
Q2
R1
FB2
Vin Q3 R2 C2 RL2
L2 Q4
Lossless Inductor Current Sensing
The iP1206 uses a lossless current sensing technique for current share purposes. The inductor current is sensed by connecting a series resistor and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor, this voltage is proportional to the inductor current. As shown in Fig. 9 the voltage across the inductor's DCR can be expressed by:
Slave Phase
Fig. 9: Loss Less inductor current sensing and current sharing the sense circuit can be treated as if only a sense resistor with the value RL1 was used.
If : R 1 * C 1 =
V RL 1 ( s ) = (V in - V out ) *
R L1 R L1 + sL 1
L1 R L1
- - - -(1 )
VC ( s ) I L1 * R L1
The mismatch of the time constants does not affect the measurements of inductor DC current, but affects the AC component of the inductor current.
V RL 1 ( s ) = I L1 * R L1
- - - -( 2 )
The voltage across the C1 can expressed by:
VC 1 ( s ) = (V in - V out ) *
sC 1 R1 + 1 sC 1
1
- - - -( 3 )
Soft-Start
The iP1206 has a programmable soft-start to control the output voltage rise and limit the inrush current during start-up. It provides a separate Soft-start function for each output. This enables the user to sequence the outputs by controlling the rise time of each output through the selection of different value soft-start capacitors. To ensure correct start-up, the soft-start sequence initiates when the Vcc and Enable rise above their threshold and generate the Power On Reset (POR) signal. Soft-start function operates by sourcing an internal current to charge an external capacitor to about 3V. Initially, the softstart function clamps the error amplifier's output of the PWM converter.
Combining equations (1),(2) and (3) result in the following expression for VC1:
VC 1 ( s ) = I L1 *
R L1 + sL 1 1 + sR 1 * C 1
- - - -( 4 )
Usually the resistor R1 and C1 are chosen so that the time constant of R1 and C1 equals the time constant of the inductor which is the inductance L1 over the inductor's DCR (RL1). If the two time constants match, the voltage across C1 is proportional to the current through L1, and
www.irf.com
2/26/2008
12
iP1206PbF
Soft-Start (cont.)
During power up, the converter output starts at zero and thus the voltage at Fb is about 0V. A current (64A) injects into the Fb pin and generates a voltage about 1.6V (64Ax25K) across the negative input of error amplifier, see Fig. 10. The magnitude of this current is inversely proportional to the voltage at the soft-start pin. The 28A current source starts to charge up the external capacitor. In the mean time, the softstart voltage ramps up, the current flowing into Fb pin starts to decrease linearly and so does the voltage at negative input of error amplifier. When the soft-start capacitor is around 1V, the voltage at the negative input of the error amplifier is approximately 0.8V. As the soft-start capacitor voltage charges up, the current flowing into the Fb pin keeps decreasing. The feedback voltage increases linearly as the injecting current decreases. The injecting current drops to zero when soft-start voltage is around 1.8V and the output voltage goes into steady state. Fig. 11 shows the theoretical operational waveforms during soft-start. The output start-up time is the time period when soft-start capacitor voltage increases from 1V to 2V. The start-up time will be dependent on the size of the external soft-start capacitor. The startup time can be estimated by:
28A Tstart = 1.8V - 1V Css
64uA
64uA
3V ISS1 = 28uA
SS1/SD1 Ihiccup1 = 3uA POR
OCP1
Seq
E/A1 Fb1
VP1
3V ISS2 = 28uA
SS2/SD2
OCP2
POR
Ihiccup2 = 3uA
E/A2 Fb2 VP2 Track
Fig. 10: Soft-Start circuit for iP1206
Output of POR 3V
1.8V
For a given start up time, the soft-start capacitor (nF) can be estimated as:
Soft-Start Voltage Current flowing into Fb pin
1V
0V 64uA 0uA
C SS
20 ( A ) * T start ( ms ) 0 . 8 (V )
- - - -( 5 )
Voltage at negative input 1.6V of Error Amp
0.8V 0.8V
For normal start up the Seq pin should be pulled high (usually can be connected to Vout3).
Voltage at Fb pin 0V
Fig. 11: Theoretical operation waveforms during soft-start
www.irf.com
2/26/2008
13
iP1206PbF
Output Voltage Sequencing Tracking and
The iP1206 can accommodate a full spectrum of user programmable tracking and sequencing options using Track, Seq, Enable and Power Good pins. Through these pins both simple voltage tracking such as that required by the DDR memory application and more sophisticated sequencing such ratiometric or simultaneously can be implemented. The Seq pin controls the internal current sources to set the power up or down sequencing, toggle this pin high for power up and toggle this pin low for power down. The Track pin is used to determine the second channel output for either ratiometric or simultaneously by using two external resistors. Fig. 12 shows how these pins are configured for different sequencing mode.
3V ISS1 = 28uA
64uA
In general the RA and RB set the output voltage for the first output and RC and RD set the output voltage for the second output. For simultaneously vs. ratiometric, RE and RF can be selected according to the table below: simultaneously Set RE = RC And RF = RD ratiometric Set RE = RA And RF = RB
SS1/SD1
OCP1
CSS1 Ihiccup1 = 3uA POR Seq Vo1 RA Fb1 E/A1
Fig. 13: Ratiometric Power up /down
RB
VP1
VREF
3V ISS2 = 28uA
64uA
SS2/SD2 Floating OCP2
Vo2 RC RD Vo1 RE RF Fb2
POR
Ihiccup2 = 3uA
Fig. 14: Simultaneously Power Up / down
E/A2
Track VP2 VREF
Fig.12: Using Seq and Track pin for different sequencing
www.irf.com
2/26/2008
14
iP1206PbF
Fault Protection
The iP1206 monitors the output voltage for over voltage protection and power good indication. It senses the Rds(on) of low side MOSFET for over current protection. It also protects the output for prebias conditions. Fig. 15 below shows the IC's operating waveforms under different fault conditions.
POR
3V 1.8V 1.0V SS
Set Voltage 90%Vfb
Pre_Bias Voltage
Vo
PGood
OCP Threshold
Iout
t0
t1 t2 t3
t4
t5
t6
t7
t8
t9
t10
t11
Fig. 15: Fault Conditions
t0 - t1: Vcc, VCH and Enable signals passed their respective UVLO threshold. Soft start sequence starts. t1 - t2: Power Good signal flags high. t1 - t3: Output voltage ramps up and reaches the set voltage. t4 - t5: OC event, SS ramps down. IC in Hiccup mode. t5- t6: OC is removed, recovery sequence, fresh SS. t6 -t7: Output voltage reaches the set voltage. t8: OVP event. HDrv turns off and LDrv Turns on. The IC latches off. t9 -t10: Manually recycled the Vcc after latched OVP.
t11: PreBias start up.
www.irf.com
2/26/2008
15
iP1206PbF
Over-Current Protection
The over current protection is performed by sensing current through the RDS(on) of low side MOSFET. This method enhances the converter's efficiency and reduce cost by eliminating a current sense resistor. As shown in Fig. 16, an external resistor (ROCSET) is connected between OCSet pin and the drain of low side MOSFET (Q2) which sets the current limit set point. When the overcurrent trip threshold is reached, the power supply output shuts down and attempts to restart, entering into the hiccup mode. The time duration between the shutdown of the output and the restart is determined by the time it takes to discharge the soft start capacitor.
OC1 IOCSET
Pre-Bias
iP1206 is able to start up into a pre-charged output, which prevents oscillation and disturbances of the output voltage. The output starts in asynchronous fashion and keeps the synchronous MOSFET off until the first gate signal for control MOSFET is generated. The figure below shows a typical Pre-Bias condition at start up. Depending on the system configuration, specific amount of output capacitors may be required to prevent discharging the output voltage. Volt
Pre-Bias Voltage (Output Voltage before startup)
Vo
iP1206
Hiccup Control
Q1
ROCSET L1 VOUT
Time
Over Voltage Protection
Over-voltage is sensed through two dedicated sense pins FBS1, FBS2. A separate OVP circuit is provided for each channel. The OVP threshold is user programmable and can be set by two external resistors. Upon overvoltage condition of either one of the outputs, the OVP forces a latched shutdown on the fault output and pulls low the low side driver. Reset is performed by recycling the Vcc or Enable. Overvoltage can be sensed either by connecting FB1s and FB2s to their corresponding outputs through separate output voltage divider resistor networks, or they can be connected directly to their corresponding feedback pins FB1 and FB2. For Type III compensation, FB1s and FB2s should be connected through voltage dividers only.
Q2
VSW PGND
Fig. 16: Connection of over current sensing resistor The duty cycle of the hiccup process is typically 5%. The hiccup is performed by charging and discharging the soft-start capacitor at a certain slope rate. As shown in Fig. 17 a 3A current source is used to discharge the soft-start capacitor. The OCP comparator resets after every soft start cycle, the converter stays in this mode until the overload or short circuit is removed. Once the condition is removed the converter will automatically recover. Refer to Fig. 24 for ROCSET selection.
28uA
22uA
Power Good
OCP
SS1 / SD
20
The iP1206 provides two separate open collector power good signals which report the status of the outputs. The outputs are sensed through the two dedicated VSEN1 and VSEN2 pins. Once the iP1206 is enabled and the outputs reach the set value (90% of set value) the power good signals go open and stay open as long as the outputs stay within the set values.These pins are open collector and need to be externally pulled high.
3uA
Fig. 17: 3uA current source for discharging soft-start capacitor during hiccup
www.irf.com
2/26/2008
16
iP1206PbF
Shutdown using Soft Start pins
The outputs can be shutdown by pulling the soft-start pin below 0.25V. This can be easily done by using an external small signal transistor. During shutdown both MOSFET drivers will be turned off. Normal operation will resume by cycling soft start pin.
Frequency Synchronization
The iP1206 is capable of accepting an external digital synchronization signal. Synchronization will be enabled by the rising edge at an external clock. Per-channel switching frequency is set by external resistor (Rt). The free running frequency oscillator frequency is twice the perchannel frequency. During synchronization, Rt is selected such that the free running frequency is 20% below the synchronization frequency. Synchronization capability is provided for both single output current share mode and dual output configuration. When unused, the sync pin will remain floating and is noise immune.
Operating Frequency Selection
The switching frequency is determined by connecting an external resistor (Rt) to ground. Fig. 18 provides a graph of oscillator frequency versus Rt. The maximum recommended channel frequency is 600kHz.
700 600 F s w (k H z ) 500 400 300 200 100 0 0 10 20 30 40 50 60 70 Rt (kOhm)
Thermal Shutdown
Temperature sensing is provided inside iP1206. The trip threshold is typically set to 135oC. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs. Thermal shutdown is not latched and automatic restart is initiated when the sensed temperature drops to normal range. There is a 20oC hysteresis in the shutdown threshold.
Fig. 18: Switching Frequency vs. External Resistor (Rt)
www.irf.com
2/26/2008
17
iP1206PbF
Application Information Design Example:
The following example is a typical application for iP1206. The application circuit is shown in page25.
Soft-Start Programming
The soft-start timing can be programmed by selecting the soft-start capacitance value. The start-up time of the converter can be calculated by using:
Vin = 12V , (13.2V , max) Vo = 1.2V I o = 30 A Vo 30mV Fs = 300kHz
CSS 20A*Tstart
- - - -( 8 )
Where Tstart is the desired start-up time (ms) For a start-up time of 5ms, the soft-start capacitor will be 0.1uF. Choose a ceramic capacitor at 0.1uF.
Output Voltage Programming
Output voltage is programmed by the reference voltage and an external voltage divider. The Fb pin is the inverting input of the error amplifier, which is internally referenced to 0.8V. The divider ratio is chosen to provide 0.8V at the Fb pin when the output is at its desired value. The output voltage is defined by using the following equation:
Input Capacitor Selection
The 180o out of phase feature will reduce the RMS value of the ripple current seen by input capacitors. This reduces numbers of input capacitors. The input capacitors selected must handle both the maximum ripple RMS at highest ambient temperature as well as the maximum input voltage. The RMS value of current ripple for duty cycle under 50% is expressed by:
I RMS =
R Vo = VREF 1 + 6 R 5
- - - -( 6 )
(I D (1- D ) + I D (1- D ) - 2I I D D )
2 1 1 1 2 2 2 2 12 1 2
- - - -( 9 )
When an external resistor divider is connected to the output as shown in Fig. 19.
VOUT iP1206
Fb1 R5 R6
Where: -IRMS is the RMS value of the input capacitor current -D1 and D2 are the duty cycle for each channel -I1 and I2 are the output current for each channel For Io=30A and D=0.10, the IRMS= 12A. Ceramic capacitors are recommended due to their peak current capabilities, they also feature low ESR and ESL at higher frequency which enhance better efficiency, Use 8x22uF, 16V ceramic capacitor from TDK (C3225X5R1C226M). For the single output application when the duty cycle is larger than 50% the following equation can be used to calculate the total RMS value input capacitor current:
Fig. 19: Typical application of the iP1206 for programming the output voltage
Equation (6) can be rewritten as:
Vref R5 = R6 V -V o ref

- - - -( 7 )
IRMS = IO (2D(1 - D) + (2 - 2D))
For the calculated values of R5 and R6 see feedback compensation section.
D > 0.5
www.irf.com
2/26/2008
18
iP1206PbF
Inductor Selection
The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor value causes a large ripple current, resulting in a smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of inductor value can be reduced to the choice of desired maximum ripple current ( i ) in the inductor. The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for desired operating ripple current can be determined using the following relation:
Output Capacitor Selection
The voltage ripple and transient requirements determine the output capacitors types and values. The criteria is normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components, these components can be described as:
Vo = Vo ( ESR) + Vo ( ESL) + Vo (C ) Vo( ESR) = I L * ESR V Vo( ESL) = in * ESL L Vo(C ) = I L 8 * Co * Fs - - - -(11)
1 i Vin - Vo = L ; t = D Fs t
Vo L = (Vin -Vo ) Vin i * Fs
Where: Vin = Maximum input voltage
Vo = Output Voltage
- - - -(10 )
Vo = Output voltage ripple IL = Inductor ripple current
Since the output capacitor has a major role in overall performance of converter and determines the result of transient response, the selection of capacitors is critical. The iP1206 can perform well with all types of capacitors. As a rule the capacitor must have low enough ESR to meet output ripple and load transient requirements, yet have high enough ESR to satisfy stability requirements. The goal for this design is to meet the voltage ripple requirement in smallest possible capacitor size. Therefore ceramic capacitors are selected due to low ESR and small size. Panasonic ECJ24YB0J107M (4*100uF, 6.3V, X5R and EIA 1210 case size) are a good choice. In the case of tantalum or low ESR electrolytic capacitors, the ESR dominates the output voltage ripple, equation (13) can be used to calculate the required ESR for the specific voltage ripple.
i = Inductor ripple current
F s= Switching frequency
t = Turn on time
D = Duty cycle
For 2-phase single output application the inductor ripple current is chosen between 10-40% of maximum phase current If i 12%(I o ), then the output inductor will be: L = 1uH The Delta MPL105-1R0IR (L1=1uH, 25A, RL1=2.3mOhm) provides a low profile inductor suitable for this application. Use the following equation to calculate C12 and R12 for current sensing: L R 12 * C 12 = 1 R L1
This results to C12=1uF and R12=402Ohm
www.irf.com
2/26/2008
19
iP1206PbF
Feedback Compensation
The iP1206 is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency and adequate phase margin (greater than 45o). The output LC filter introduces a double pole, - 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180o (see Fig. 20). The resonant frequency of the LC filter expressed as follows:
FESR =
1 2 * ESR* Co
- - - -(13)
VOUT R6 Fb R5 VREF
Gain(dB)
E/A
Comp Ve C9 R4 CPOLE
H(s) dB
FLC =
1 2 Lo Co
180o
- - - -(12)
FZ
Frequency
phase shift just from Since we already have the output filter, the system risks being unstable.
Fig. 21: TypeII compensation network and its asymptotic gain plot The transfer function (Ve/Vo) is given by:
R5 1 + sR4C9 * H (s) = gm * R5 + R6 sC9 - - - -(14)
Gain 0dB -40dB/decade
Phase 0
The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by:
FLC Frequency
FLC Frequency
-180
[H (s)] = gm *
Fz =
Fig. 20: Gain and Phase of LC filter The iP1206's error amplifier is a differential-input transconductance amplifier. The output is available for DC gain control or AC phase compensation. The E/A can be compensated either in type II or type III compensation. When it is used in type II compensation the transconductance properties of the E/A become evident and can be used to cancel one of the output filter poles. This will be accomplished with a series RC circuit from Comp pin to ground as shown in Fig. 21. This method requires that the output capacitor should have enough ESR to satisfy stability requirements. In general the output capacitor's ESR generates a zero typically at 5kHz to 50kHz which is essential for an acceptable phase margin. The ESR zero of the output capacitor expressed as follows:
R5 * R4 R5 + R6 - - - -(16)
- - - -(15)
1 2 * R4 *C9
The gain is determined by the voltage divider and E/A's transconductance gain. First select the desired zero-crossover frequency (Fo): Fo > FESR and Fo (1/5 ~ 1/10) * Fs Use the following equation to calculate R4:
R4 =
Where:
Vosc * Fo * FESR * (R5 + R6 ) 2 Vin * FLC * R5 * gm
- - - -(17)
Vin = Maximum Input Voltage Vosc = Oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter gm = Error Amplifier Transconductance
www.irf.com
2/26/2008
20
iP1206PbF
To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole:
Fz = 75%FLC Fz = 0.75* 1 2 Lo *Co
1 2 * R4 * Fz
ZIN
- - - -(18)
VOUT C10 R8 R6 Fb R5 R7
C12 C11 Zf
Using equations (16) and (18) to calculate C9.
C9 =
E/A
Comp
Ve
One more capacitor is sometimes added in parallel with C9 and R4. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by:
FP = 1 C *C 2 * R4 * 9 POLE C9 + CPOLE
Gain(dB)
VREF
H(s) dB
FZ1
FZ2
FP2
FP3
Frequency
The pole sets to one half of switching frequency which results in the capacitor CPOLE:
CPOLE = 1
Fig. 22: Compensation network with local feedback and its asymptotic gain plot As known, transconductance amplifiers have high impedance (current source) outputs, therefore, care should be taken when loading the E/A output. It may exceed its source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the necessary range. The compensation network has three poles and two zeros and they are expressed as follows:
FP1 = 0 FP 2 = FP 3 = 1 2 * R8 * C10 1 1 C * C 2 * R7 * C12 2 * R7 11 12 C + C 11 12 1 2 * R7 * C11 1 1 2 * C10 * (R6 + R8 ) 2 * C10 * R6
* R4 * Fs -
1 C9
1 * R4 * Fs
Fs 2 For a general solution for unconditionally stability and any type of output capacitors, in a wide range of ESR values we should implement local feedback with a compensation network (typeIII). The typically used compensation network for voltage-mode controller is shown in Fig. 22. For FP <<
In such configuration, the transfer function is given by:
Ve 1 - g m Zf = Vo 1 + g m ZIN
The error amplifier gain is independent of the transconductance under the following condition:
Fz1 = Fz 2 =
g m * Zf >> 1 and g m * Z in >> 1
- - - -(19)
By replacing Zin and Zf according to figure 15, the transformer function can be expressed as:
1 (1 + sR7C11 ) * [1 + sC10 (R6 + R8 )] H (s ) = * sR6 (C11 + C12 ) C11 * C12 1 + sR7 C + C * (1 + sR8C10 ) 11 12
Cross over frequency is expressed as:
Fo = R7 * C10 * Vin 1 * Vosc 2 * Lo * Co
www.irf.com
2/26/2008
21
iP1206PbF
Based on the frequency of the zero generated by output capacitor and its ESR versus crossover frequency, the compensation type can be different. The table below shows the compensation types and location of crossover frequency.
Compensator type TypII(PI)
FESR vs. Fo
Output capacitor Electrolytic , Tantalum Tantalum, ceramic Ceramic
The following design rules will give a crossover frequency approximately one-sixth of the switching frequency. The higher the band width, the potentially faster the load transient response. The DC gain will be large enough to provide high DC-regulation accuracy (typically -5dB to -12dB). The phase margin should be greater than 45o for overall stability. Desired Phase Margin: max = 3
1 - Sin 1 + Sin FZ 2 = 10.72kHz FZ 2 = Fo * FP2 = Fo * 1 + Sin 1 - Sin FP2 = 81.2kHz
FLCTypeIII(PID) Method A TypeIII(PID) Method B
Table1- The compensation type and location of FESR versus Fo The details of these compensation types are discussed in application note AN-1043 which can be downloaded from the IR Web-Site. For this design we have: Vin=12V Vo=1.2V Vosc=1.25V Vref=0.8V gm=2800umoh Lo=1uH, DCR=2.4mOhm Co=15x22uF, ESR= 0.33mOhm Fs=300kHz These result to:
FLC=10.73kHz
(Replace L to L/2 in formula#14 for current share configuration)
Select: FZ1 = 0.5 * FZ 2 and FP3 = 0.5* Fs R7 2 ; R7 0.72K; Select: R7 = 6.81K gm
CalculateC11 , C12 and C10 : C11 = 1 ; C11 = 4.36nF, Select: C11 = 5.6nF 2 * FZ1 * R 7 1 ; C12 = 155pF, Select: C12 = 100pF 2 * FP3 * R7 2 * Fo * Lo * Co *Vosc ; C10 = 0.85nF, R7 *Vin
C12 =
C10 =
Select: C10 = 1nF Calculate R8 , R6 and R5 : R8 = 1 ; R8 = 1.96K, Select: R8 = 2K 2 * C10 * FP2 1 - R8 ; R6 = 13.9K, Select: R6 = 16.9K 2 * C10 * FZ 2 Vref Vo - Vref * R6 ; R5 = 39.2K, Select: R5 = 39.2K
FESR=1.46MHz Fs/2=150kHz
Select crossover frequency:
Fo < FESR and Fo (1/5 ~ 1/10) * Fs Fo=40kHz
R6 =
Since: FLCR5 =
www.irf.com
2/26/2008
22
iP1206PbF
Compensation for (slave channel) Current Loop
The slave error amplifier is differential transconductance amplifier, in 2-phase configuration the main goal for the slave channel feedback loop is to control the inductor current to match the master channel inductor current as well provides highest bandwidth and adequate phase margin for overall stability. The following analysis is valid for both using external current sense resistors and using DCR of inductor. The transfer function of power stage is expressed by: Select a zero frequency for current loop (Fo2) 1.5 times larger than zero cross frequency for voltage loop (Fo1).
FO2 1.5% * FO1
H (FO2 ) = gm * Rs1 * R2 *
Vin =1 2 * FO2 * L2 *Vosc
- - - -( 22 )
From (22), R2 can be expressed as:
I (s) Vin G(s) = L2 = Ve sL2 *Vosc
Where: Vin=Input voltage L2=Output inductor Vosc=Oscillator Peak Voltage
R2 =
- - - -( 20 )
1 2 * FO2 * L2 *Vosc * gm * Rs1 Vin
- - - -( 23 )
Vin=12V Vosc=1.25V gm=2800umoh L2=1uH Rs1=DCR=2.4mOhm Fo2=60kHz This results to : R2=5.84K The power stage of current loop has a dominant pole (Fp) at frequency expressed by:
FP =
Comp2 Ve R2
As shown the G(s) is a function of inductor current. The transfer function for compensation network is given by equation (21), when using a series RC circuit as shown in Fig 23.
IL2 L2 Fb2 RS2 Vp2 RS1 L1 IL1 E/A2
Req 2 * L2
Req = Rds(on1) * D + Rds(on2 ) * (1 - D) + RL
C2
Where Rds(on1) is the on-resistance of control FET, Rds(on2) is the on-resistance of synchronous FET, RL is the DCR of output inductance and D is the duty cycle Req=9.48mOhm
Req = Rds(on) + RL + Rs
Fig. 23: The Compensation network for current loop
D(s) =
Ve (s) R 1 + sC2 R2 = gm * s1 * Rs 2 Rs 2 sC2
- - - -( 21)
The loop gain function is:
H(s) = [G(s) * D(s) * Rs2 ]
R 1 + sR2C2 Vin * H(s) = Rs 2 * gm * s1 * Rs 2 sC2 sL2 * Vosc
Set the zero of compensator at 10 times the dominant pole frequency FP, the compensator capacitor, C2 can be expressed as:
Fz = 10 * FP C2 = 1 2 * R2 * Fz
C2=1nF All designs should be tested for stability to verify the calculated values.
www.irf.com
2/26/2008
23
iP1206PbF
Programming the Current-Limit
The Current-Limit threshold can be set by connecting a resistor (ROCSET) from drain of low side MOSFET to the OCSet pin. The resistor value can be obtained by using Fig. 24. It is important to pay careful attention to the layout of this resistor. It is recommended to place this resistor close to the IC and away from possible noisy traces. A small ceramic capacitor from this pin to ground can also be place for noise rejection purposes. The trip current Itrip is given by:
I trip = I max + I L,Peak - - - -( 7 ) where I max = Maximum DC load current* 1.5 I L,Peak= Peak Inductor Current For a maximum DC load current of 8.5A and an inductor ripple of 3A I L,Peak = 1.5A I trip = 8.5 * 1.5 +1.5A = 14.25A From Fig. 24 we get ROCSET = 5.23K
i Note: I L,Peak = = 2
(Vin -Vo )
Vo Vin L * Fs 2
13
12
11
10
Current Limit Resistor (kOhms)
9
8
7
6
5
4
3
2
1 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Peak Inductor Current (A)
Fig. 24: ROCSET selection from Peak Inductor Current
www.irf.com
2/26/2008
24
iP1206PbF
Typical Application Circuit
12V
Vo = 1.2V
Fig. 25a: Typical Single Output Application circuit for 12V to 1.2V @ 30A
Fig. 25b: Typical Dual Output Application circuit for 12V to 2.5V @ 15A , 12V to 1.5V@ 15A
www.irf.com
2/26/2008
25
iP1206PbF
Recommended PCB Footprint
Fig. 26
www.irf.com
2/26/2008
26
26
iP1206PbF
PGND15
Fig. 27 Top component and via placement (Topside, transparent view down)
PGND4
PGND6
PGND13
PCB Layout Guidelines The following guidelines are recommended to reduce the parasitic values and optimize overall performance. * All pads on the iP1206 footprint design need to be Solder-mask defined (see Figure 26). Also refer to International Rectifier application notes AN1028 and AN1029 for further footprint design guidance. * Place as many vias around the Power pads (VIN, VSW, and PGND) for both electrical and optimal thermal performance. * Vias in between the different power pads may overlap the pad opening and solder mask edge without the need to plug the via hole. Vias with a 13mil drill hole and 25mil capture pad were used in this example. * A minimum of six 10F, X5R, 16V ceramic capacitors per iP1206 are recommended for the lowest loss due to input capacitor ESR. * Placement of the ceramic input capacitors is critical to optimize switching performance. In cases where there is a space constraint on the top layer capacitors C3,C4, C7 and C8 can be placed on the bottom layer directly below the footprints of C1, C2, C5 and C6. * Dedicate at least two layers for PGND only. * Duplicate the Power Nodes on multiple layers (refer to AN1029). * Refer to AN-1030 for information on applying IPOWIR products in your thermal environment for Safe Operation.
www.irf.com
2/26/2008
27
iP1206PbF
Mechanical Outline
TOP VIEW
.006 [0.15] C 2X 6 B A NOTES: DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. DIMENSIONS ARE SHOWN IN INCHES[MILLIMETERS]. CONTROLLING DIMENSION: INCHES LAND PAD OPENINGS. PRIMARY DATUM C (SEATING PLANE) IS DEFINED BY THE LAND PAD OPENINGS. 6 BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY. 7. NOT TO SCALE. 1. 2. 3. 4. 5
CORNER ID
2X
6
.006 [0.15] C 27X 23X .005 [0.12] C
CORNER ID
5C
6X
2X
SIDE VIEW
Fig. 28
www.irf.com
2/26/2008
28
28
iP1206PbF
Tape and Reel Information
Fig. 29
www.irf.com
2/26/2008
29
iP1206PbF
Recommended Solder Paste Stencil Design
The recommended reflow peak temperature is 260oC. The total furnace time is approximately 5 minutes with approximately 10 seconds at peak temperature.
Fig. 30
Part Marking
Pin 1 Identifier International Rectifier Logo Assembly Code
Fig. 31
Date Code (YYWW) YY= Year WW = Week Part Number Factory Code
IR WORLD HEADQUARTERS: 233 Kansas Street., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed for the Industrial market. Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 08/08/2007
www.irf.com
2/26/2008
30

▲Up To Search▲

Price & Availability of IP1206TRPBF

	To Download IP1206TRPBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .